MLIR letter-D vector versions are portrayed while the (n-1)-D arrays of 1-D vectors when reduced to help you LLVM

The fresh new implication of your actual HW limitations to the coding model is actually this 1 don’t directory dynamically across the gear reports: an enter document is also basically not be detailed dynamically. Simply because the latest sign in matter is fixed and one either must unroll clearly discover fixed check in amounts otherwise wade owing to thoughts. It is a constraint familiar to CUDA programmers: when declaring a private drift an excellent ; and you may then indexing having an active worthy of causes very-entitled local memory need (i.age. roundtripping to thoughts).

Implication toward codegen ¶

So it raises the results with the fixed compared to vibrant indexing talked about in past times: extractelement , insertelement and you can shufflevector on n-D vectors during the MLIR merely service static indices. Vibrant indicator are only supported on the extremely minor step 1-D vector although not the latest exterior (n-1)-D . For other instances, direct stream / places are expected.

1. Loops to vector opinions was secondary handling out of vector thinking, they want to run using direct weight / shop operations more than n-D vector sizes.
2. Immediately following a keen letter-D vector sort of was stacked towards the an enthusiastic SSA really worth (that may otherwise might not inhabit n documents, having otherwise versus spilling, whenever eventually decreased), it may be unrolled so you’re able to quicker k-D vector items and processes one match the latest HW. So it amount of MLIR codegen is comparable to check in allowance and you can spilling one can be found far after from the LLVM pipeline.
3. HW could possibly get help >1-D vectors which have intrinsics for indirect handling in these vectors. These may become directed owing to direct vector_cast functions of MLIR k-D vector types and processes to help you LLVM 1-D vectors + intrinsics.

Rather, i believe yourself reducing so you’re able to an effective linearized abstraction hides away the fresh new codegen complexities linked to thoughts accesses giving a false impact out-of enchanting active indexing across data. Alternatively i like to generate people really specific during the MLIR and you may ensure it is codegen to explore tradeoffs. Various other HW will require different tradeoffs regarding items doing work in actions step one., dos. and you can step 3.

Decisions generated from the MLIR top get effects within good much afterwards stage inside the LLVM (after register allotment). We do not consider to reveal concerns related to modeling out-of check in allocation and you may spilling in order to MLIR clearly. As an alternative, for each and every address tend to introduce some “good” address operations and you will n-D vector systems, with the can cost you one PatterRewriters at the MLIR level could be in a position to target. Particularly costs in the MLIR height could well be conceptual and you can used to own ranks, perhaps not to possess direct abilities modeling. Down the road such can cost you could be read.

Implication toward Lowering so you’re able to Accelerators ¶

To target accelerators that support higher dimensional vectors natively, we can start from either 1-D or n-D vectors in MLIR and use vector.cast to flatten the most minor dimensions to 1-D vector where K is an appropriate constant. Then, the existing lowering to LLVM-IR immediately applies, with extensions for accelerator-specific intrinsics.

It is the role of an Accelerator-specific vector dialect (see codegen flow in the figure above) to lower the vector.cast . Accelerator -> LLVM lowering would then consist of a bunch of Accelerator -> Accelerator rewrites to perform the casts composed with Accelerator -> LLVM conversions + intrinsics that operate on 1-D vector .

Some of those rewrites may need extra handling, especially if a reduction is involved. For example, vector.cast %0: vector to vector when K != K1 * … * Kn and some arbitrary irregular vector.cast %0: vector<4x4x17xf32> to vector may introduce masking and intra-vector shuffling that may not be worthwhile or even feasible, i.e. infinite cost.

However vector.cast %0: vector to vector when K = K1 * … * Kn should be close to a noop.